Design of Fault Tolerance x86 Server with FPGA or QEMU

By | 2019年5月27日

1. Background

Since the MicroBlaze provides the lockstep feature, so finally we can make a POC.

2. MicroBlaze FT Test

3. Server FT Test via MicroBlaze FT controller

4. QEMU with COLO

[1] Triple Modular Redundancy: https://www.xilinx.com/support/documentation/ip_documentation/tmr/v1_0/pg268-tmr.pdf

[2] Fault Tolerance Technique for Dynamically Reconfigurable Processor: https://pdfs.semanticscholar.org/2e98/b34ee8736eba7747b223c333de5739a6e601.pdf

[3] Xilinx Reduces Risk and Increases Efficiency for IEC61508 and ISO26262 Certified Safety Applications: https://www.xilinx.com/support/documentation/white_papers/wp461-functional-safety.pdf

[4] Spartan-6 FPGA Dual-Lockstep MicroBlaze Processor with Isolation Design Flow: https://www.xilinx.com/support/documentation/application_notes/xapp584-dual-lockstep-microblaze-IDF.pdf

[5] MicroBlaze Processor Reference Guide: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug984-vivado-microblaze-ref.pdf

One thought on “Design of Fault Tolerance x86 Server with FPGA or QEMU

发表评论

电子邮件地址不会被公开。